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A Cooperative Algorithm for Stereo Matching and Occlusion Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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SMBV '01 Proceedings of the IEEE Workshop on Stereo and Multi-Baseline Vision (SMBV'01)
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
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ICCV '05 Proceedings of the Tenth IEEE International Conference on Computer Vision (ICCV'05) Volume 1 - Volume 01
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International Journal of Computer Vision
Adaptive Support-Weight Approach for Correspondence Search
IEEE Transactions on Pattern Analysis and Machine Intelligence
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A code refinement methodology for performance-improved synthesis from C
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary
ECOOP '08 Proceedings of the 22nd European conference on Object-Oriented Programming
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IEEE Transactions on Circuits and Systems for Video Technology
DAISY: An Efficient Dense Descriptor Applied to Wide-Baseline Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
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Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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ECCV'06 Proceedings of the 9th European conference on Computer Vision - Volume Part IV
Cost Aggregation and Occlusion Handling With WLS in Stereo Matching
IEEE Transactions on Image Processing
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IEEE Transactions on Circuits and Systems for Video Technology
Improving high level synthesis optimization opportunity through polyhedral transformations
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Journal of Real-Time Image Processing
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FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high--often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4× to 126× speedup over the software version. The stereo matching algorithms achieve between 3.5× and 67.9× speedup over software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.