Real-time high-definition stereo matching on FPGA
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A real-time stereo vision system using a tree-structured dynamic programming on FPGA
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Low-cost FPGA stereo vision system for real time disparity maps calculation
Microprocessors & Microsystems
High-level synthesis: productivity, performance, and software constraints
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Hardware design considerations for edge-accelerated stereo correspondence algorithms
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Facing the Multicore-Challenge II
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm
Computer Vision and Image Understanding
A precise real-time stereo algorithm
Proceedings of the 27th Conference on Image and Vision Computing New Zealand
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Real-time architecture for a robust multi-scale stereo engine on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Efficient and high performance FPGA-based rectification architecture for stereo vision
Microprocessors & Microsystems
Evaluation of stereo correspondence algorithms and their implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
Fast and Accurate Stereo Vision System on FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies.