Journal of Algorithms
Eigenfaces vs. Fisherfaces: Recognition Using Class Specific Linear Projection
IEEE Transactions on Pattern Analysis and Machine Intelligence
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Digital Signal Processing: A Computer-Based Approach
Digital Signal Processing: A Computer-Based Approach
Dynamic Vision: From Images to Face Recognition
Dynamic Vision: From Images to Face Recognition
Optimal evaluation of pairs of bilinear forms
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
The Multiple Wordlength Paradigm
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Multiplierless implementation of 2-D FIR filters
Integration, the VLSI Journal
A Novel 2D Filter Design Methodology for Heterogeneous Devices
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Architectures for generalized 2D FIR filtering using separable filter structures
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wordlength optimization for linear digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploration of heterogeneous FPGAs for mapping linear projection designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Domain-Specific Optimization of Signal Recognition Targeting FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
Journal of Systems Architecture: the EUROMICRO Journal
Self-Reconfigurable Constant Multiplier for FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Real-Time Image Processing
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Many image processing applications require fast convolution of an image with one or more 2D filters. Field-Programmable Gate Arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the heterogeneous nature of modern reconfigurable devices is not usually considered during design optimization. This article proposes an algorithm that explores the space of possible implementation architectures of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in a heterogeneous device. This is achieved by exploring the heterogeneous nature of modern reconfigurable devices using a Singular Value Decomposition based algorithm, which provides an efficient mapping of filter's implementation requirements to the heterogeneous components of modern FPGAs. In the case of multiple 2D filters, the proposed algorithm also exploits any redundancy that exists within each filter and between different filters in the set, leading to designs with minimized area. Experiments with real filter sets from computer vision applications demonstrate an average of up to 38% reduction in the required area.