Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Exploration of heterogeneous FPGAs for mapping linear projection designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
Journal of Systems Architecture: the EUROMICRO Journal
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In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the heterogeneous nature of modern reconfigurable devices is not usually considered during design optimization. This paper proposes an algorithm that explores the implementation architecture of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in a heterogeneous device. Experiments show that the proposed algorithm can achieve a reduction in the required area in a range of 34% to 70% when compared to current techniques.