Optimizing Hardware Function Evaluation
IEEE Transactions on Computers
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimum wordlength search using sensitivity information
EURASIP Journal on Applied Signal Processing
Design and implementation of numerical linear algebra algorithms on fixed point DSPs
EURASIP Journal on Advances in Signal Processing
Proceedings of the 45th annual Design Automation Conference
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Externally linear time invariant digital signal processors
IEEE Transactions on Signal Processing
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
High-level synthesis under fixed-point accuracy constraint
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Robust Software Partitioning with Multiple Instantiation
INFORMS Journal on Computing
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are proposed, one which guarantees an optimum set of wordlengths for each internal variable, and one which is a heuristic approach. Both techniques allow the user to tradeoff implementation area for arithmetic error at system outputs. Optimality (with respect to the area and error estimates) is guaranteed through modeling as a mixed integer linear program. It is demonstrated that the proposed heuristic leads to area improvements of 6% to 45% combined with speed increases compared to the optimum uniform wordlength design. In addition, the heuristic reaches within 0.7% of the optimum multiple wordlength area over a range of benchmark problems.