Performance limitations in parallel processor simulations
Transactions of the Society for Computer Simulation International
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations
IEEE Transactions on Computers
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Faithful Bipartite ROM Reciprocal Tables
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Parameterized High Throughput Function Evaluation for FPGAs
Journal of VLSI Signal Processing Systems
The Design Warrior's Guide to FPGAs
The Design Warrior's Guide to FPGAs
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of symbolic computer algebra in high-level data-flow synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wordlength optimization for linear digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
RAT: a methodology for predicting performance in application design migration to FPGAs
HPRCTA '07 Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07
Modular design and implementation of FPGA-based tap-selective maximum-likelihood channel estimator
WSEAS Transactions on Signal Processing
Accelerating seismic computations using customized number representations on FPGAs
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance special function unit for programmable 3-D graphics processors
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Square-rich fixed point polynomial evaluation on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x) typically consists of range reduction and the actual evaluation on a small convenient interval such as [0,\pi/2) for \sin(x). We investigate the impact of hardware function evaluation with range reduction for a given range and precision of x and f(x) on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point \sin(x), \log(x), and \sqrt{x} accurate to one unit in the last place using MATLAB and ASC, A Stream Compiler for Field-Programmable Gate Arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million Application-Specific Integrated Circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits.