Computer Approximations
Software Manual for the Elementary Functions (Prentice-Hall series in computational mathematics)
Software Manual for the Elementary Functions (Prentice-Hall series in computational mathematics)
Approximating Elementary Functions with Symmetric Bipartite Tables
IEEE Transactions on Computers
Implementation of the Exponential Function in a Floating-Point Unit
Journal of VLSI Signal Processing Systems
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
IEEE Transactions on Computers
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root
IEEE Transactions on Computers
Accurate Function Approximations by Symmetric Table Lookup and Addition
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Parameterized High Throughput Function Evaluation for FPGAs
Journal of VLSI Signal Processing Systems
High-Speed Function Approximation Using a Minimax Quadratic Interpolator
IEEE Transactions on Computers
Automating custom-precision function evaluation for embedded processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Optimizing Hardware Function Evaluation
IEEE Transactions on Computers
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.00 |
A different approach to hardware evaluation of elementary functions for high-precision floating-point numbers (in particular, the extended double precision format of the IEEE standard P754) is examined. The evaluation is based on rational approximations of the elementary functions, a method which is commonly used in scientific software packages. A hardware model is presented of a floating-point numeric coprocessor consisting of a fast adder and a fast multiplier, and the minimum hardware required for evaluation of the elementary functions is added to it. Next, rational approximations for evaluating the elementary functions and testing the accuracy of the results are derived. The calculation time of these approximations in the proposed numeric processor is then estimated. It is concluded that rational approximations can successfully complete with previously used methods when execution time and silicon area are considered.