Hardwired polynomial evaluation
Journal of Parallel and Distributed Computing - Parallelism in Computer Arithmetic
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Parallelism exposure and exploitation in programs
Parallelism exposure and exploitation in programs
Parallel Montgomery Multiplication in GF (2^k) Using Trinomial Residue Arithmetic
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Optimizing Hardware Function Evaluation
IEEE Transactions on Computers
Optimizing Logarithmic Arithmetic on FPGAs
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
On the Parallel Evaluation of Polynomials
IEEE Transactions on Computers
Organization of computer systems: the fixed plus variable structure computer
IRE-AIEE-ACM '60 (Western) Papers presented at the May 3-5, 1960, western joint IRE-AIEE-ACM computer conference
Generalizations of Horner's rule for polynomial evaluation
IBM Journal of Research and Development
Optimal algorithms for parallel polynomial evaluation
Journal of Computer and System Sciences
High-performance hardware operators for polynomial evaluation
International Journal of High Performance Systems Architecture
Long Integers and Polynomial Evaluation with Estrin's Scheme
SYNASC '11 Proceedings of the 2011 13th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing
Efficient Large Integer Squarers on FPGA
FCCM '13 Proceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
Hi-index | 0.00 |
Polynomial evaluation is important across a wide range of application domains, so significant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial computation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an efficient polynomial evaluation algorithm, which reforms the evaluation process to include an increased number of squaring steps. By using a squarer design that is more efficient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5th degree polynomials.