Parallelism exposure and exploitation in programs
Parallelism exposure and exploitation in programs
On the Addition of Binary Numbers
IEEE Transactions on Computers
Optimal algorithms for parallel polynomial evaluation
SWAT '71 Proceedings of the 12th Annual Symposium on Switching and Automata Theory (swat 1971)
Organization of computer systems: the fixed plus variable structure computer
IRE-AIEE-ACM '60 (Western) Papers presented at the May 3-5, 1960, western joint IRE-AIEE-ACM computer conference
Generalizations of Horner's rule for polynomial evaluation
IBM Journal of Research and Development
New algorithms and lower bounds for the parallel evaluation of certain rational expressions
STOC '74 Proceedings of the sixth annual ACM symposium on Theory of computing
The Parallel Evaluation of Arithmetic Expressions Without Division
IEEE Transactions on Computers
Parallelism and Array Processing
IEEE Transactions on Computers
Square-rich fixed point polynomial evaluation on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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If an unlimited number of processors is available, then for any given number of steps s, s=1, polynomials of degree as large as C2n-dcan be evaluated, where C= v2 and d v2s. This implies polynomials of degree can be evaluated in log2n+v2log2n +0(1) steps. Various techniques for the evaluation of polynomials in a "reasonable number" of "steps" are compared with th