Two-Dimensional Convolution on a Pyramid Computer
IEEE Transactions on Pattern Analysis and Machine Intelligence
On the Communication Complexity of Generalized 2-D Convolution on Array Processors
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Convolution on Mesh Connected Multicomputers
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallelism in computer vision: a review
Parallel algorithms for machine intelligence and vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
Using and designing massively parallel computers for artificial neural networks
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Programmable active memories: a performance assessment
Proceedings of the 1993 symposium on Research on integrated systems
Digital system design using field programmable gate arrays
Digital system design using field programmable gate arrays
IEEE Spectrum
Simulating Artificial Neural Networks on Parallel Architectures
Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering
Learning Texture Discrimination Masks
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Real-Time Matching System for Large Fingerprint Databases
IEEE Transactions on Pattern Analysis and Machine Intelligence
IEEE Spectrum
Computer Vision
Billion-Transistor Architectures
Computer
NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems
IEEE Transactions on Parallel and Distributed Systems
Building Blocks for Computer Vision Systems
IEEE Expert: Intelligent Systems and Their Applications
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
FPGA-based high performance page layout segmentation
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Computer vision algorithms on reconfigurable logic arrays
Computer vision algorithms on reconfigurable logic arrays
System-on-programmable-chip implementation for on-line face recognition
Pattern Recognition Letters
Cost-effective video filtering solution for real-time vision systems
EURASIP Journal on Applied Signal Processing
Design and evaluation of a hardware/software FPGA-based system for fast image processing
Microprocessors & Microsystems
A hardware architecture for real-time video segmentation utilizing memory reduction techniques
IEEE Transactions on Circuits and Systems for Video Technology
Fine grain pipeline systems for real-time motion and stereo-vision computation
International Journal of High Performance Systems Architecture
Journal of Real-Time Image Processing
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Computer vision algorithms are natural candidates for high performance computing systems. Algorithms in computer vision are characterized by complex and repetitive operations on large amounts of data involving a variety of data interactions (e.g., point operations, neighborhood operations, global operations). In this paper, we describe the use of the custom computing approach to meet the computation and communication needs of computer vision algorithms. By customizing hardware architecture at the instruction level for every application, the optimal grain size needed for the problem at hand and the instruction granularity can be matched. A custom computing approach can also reuse the same hardware by reconfiguring at the software level for different levels of the computer vision application. We demonstrate the advantages of our approach using Splash 2驴a Xilinx 4010-based custom computer.