Analog VLSI and neural systems
Analog VLSI and neural systems
Performance of optical flow techniques
International Journal of Computer Vision
Performance of phase-based algorithms for disparity estimation
Machine Vision and Applications - Special issue on performance evaluation
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
Accuracy vs efficiency trade-offs in optical flow algorithms
Computer Vision and Image Understanding
The optimum pipeline depth for a microprocessor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Stability of Phase Information
IEEE Transactions on Pattern Analysis and Machine Intelligence
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Motion-Driven Segmentation by Competitive Neural Processing
Neural Processing Letters
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm
Machine Vision and Applications
Hardware implementation of optical flow constraint equation using FPGAs
Computer Vision and Image Understanding
Variational optical flow computation in real time
IEEE Transactions on Image Processing
Real-Time System for High-Image Resolution Disparity Estimation
IEEE Transactions on Image Processing
FPGA-based real-time optical-flow system
IEEE Transactions on Circuits and Systems for Video Technology
Optimization strategies for high-performance computing of optical-flow in general-purpose processors
IEEE Transactions on Circuits and Systems for Video Technology
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Image processing systems require high computational load that motivates the design of specific hardware architectures in order to arrive at real-time platforms. We adopt innovative design techniques based on the intensive utilisation of the inherent parallelism available on devices based on reconfigurable hardware. We customise fine-grain pipelining and superscalar units to implement specific computing architectures for motion and stereo-vision computing circuits. This high parallelism level allows us to achieve a high data throughput (one pixel feature estimation per clock cycle). This paper extensively uses these techniques for designing high performance image processing systems which fit early cognitive vision models specifications. Furthermore, it highlights the necessity of on-chip integration mechanisms, since the data throughput (bandwidth requirements) of the full system requires a very large bandwidth.