Design and FPGA implementation of lifting scheme for 2D-DWT using wavepipelining

Authors:
G. Seetharaman;B. Venkataramani;G. Lakshminarayanan
Affiliations:
Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, India;Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, India;Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, India
Venue:
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Year:
2005

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Abstract

In this paper, a hybrid scheme is proposed for the implementation of two level 2D-DWT using lifting scheme. Two filter banks consisting of two filters each are used for the implementation of both horizontal and vertical filters. Each of the filter banks are implemented using the lifting scheme. The individual lifting blocks are implemented using wavepipelining and are interconnected with registers. An automation procedure is proposed for tuning the parameters of the wavepipelined circuit. The multipliers in the lifting blocks are implemented using Baugh-Wooley constant coefficient multiplier scheme (BW-KCM). For verifying the efficacy of the scheme proposed, both one level and two level 2-D DWT schemes for sub images of size 32×32 are implemented on Xilinx XC2S150 device. The results for the hybrid scheme are compared with that obtained using non-pipelined and pipelined approaches. For the one level 2D DWT, the hybrid scheme requires the same area but is faster than nonpipelined scheme by a factor of 1.4. The pipelined scheme using the pipelined BW-PKCM is faster than the hybrid scheme by a factor of 1.2 at the cost of increase in the no. of registers by a factor of 2.73. The delay-power product is lower for hybrid scheme by a factor of 2 than the pipelined scheme. The two level 2D DWT for both pipelined and non pipelined schemes are implemented. The implementation of hybrid scheme for 2 level 2 D DWT is under progress. The technique proposed in this paper is also applicable for ASICs and FPGAs from other vendors.