Optimisation techniques for the system on chip implementation of JPEG encoder
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Fixed-point IDCT without multiplications based on B.G. Lee's algorithm
Digital Signal Processing
Scaled AAN for fixed-point multiplier-free IDCT
EURASIP Journal on Advances in Signal Processing
System-on-Chip Subband Decomposition Architectures for Ultrasonic Detection Applications
Journal of Signal Processing Systems
| Hi-index | 35.68 |
In this paper, efficient architectures for realizing the recursive discrete cosine transform (DCT) and the recursive inverse DCT (IDCT) are proposed. By respectively folding the inputs of the DCT and the outputs of the IDCT, efficient formulations of the DCT and IDCT are derived to construct the transform kernels. The data throughput per transformation is twice that of the existing methods by spending only half of the computational cycles used by the single folding algorithms. To further improve efficiency, the double folding recursive architectures of the DCT and IDCT are developed. The computational cycles of the DCT are half of the single folding method, and the data throughput of the IDCT is twice that of the single folding method. The regular and modular properties of the proposed recursive architectures are suitable for very large scale integration (VLSI) implementation. With high throughput advantage, the proposed structures could be implemented with less power consumption, which could be applied to low rate video in mobile and portable information appliances.