Design and Implementation of an Image CoProcessor

Authors:
R. Ebrahimi Atani;S. Mirzakuchaki;S. Ebrahimi Atani
Affiliations:
EE Department, IUST, Narmak, Tehran, Iran 16846;EE Department, IUST, Narmak, Tehran, Iran 16846;Department of Mathematics, Guilan University, Faculty of Science, Rasht, Iran
Venue:
ICISP '08 Proceedings of the 3rd international conference on Image and Signal Processing
Year:
2008

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Abstract

This paper presents a novel DA based 2D DCT/DST coprocessor architecture for the synchronous design in a Xilinx FPGA device. A 1.2V, 90nm triple-oxide technology, Virtex-IV FPGA is used for final implementation and maximum operating frequency of 117 MHz is achieved. Using XPower toolbox, the total dynamic power consumption of 393 mW is measured. The paper presents the trade-offs involved in designing the architecture, and the design for performance issues.