Improved CLA scheme with optimized delay
Journal of VLSI Signal Processing Systems - Special issue: computer arithmetic
Gro¨bner bases: a computational approach to commutative algebra
Gro¨bner bases: a computational approach to commutative algebra
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Using symbolic algebra in algorithmic level DSP synthesis
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient Boolean division and substitution using redundancy addition and removing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Optimization of polynomial datapaths using finite ring algebra
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Progressive decomposition: a heuristic to structure arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Code transformation and instruction set extension
ACM Transactions on Embedded Computing Systems (TECS)
Iterative layering: optimizing arithmetic circuits by structuring the information flow
Proceedings of the 2009 International Conference on Computer-Aided Design
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths
Integration, the VLSI Journal
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Proceedings of the 50th Annual Design Automation Conference
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The optimization of arithmetic circuits has always been essentially a manual task: arithmetic experts study the best architectures for arithmetic components and write libraries of generators, and designers instantiate library components and rely on logic synthesizers to obtain good implementations. In this paper we look at the capabilities of commercial synthesizers when it comes to arithmetic circuits, and observe that they are essentially unable to switch from one arithmetic architecture to another (e.g., from a ripple-carry to a carry-lookahead adder). Therefore, users relying on logic synthesis miss most optimization potentials. We therefore investigate algorithms for factorization which can prepare structured VHDL or Verilog for synthesizers to implement, and show first steps into pruning the search space from many irrelevant or equivalent solutions. Our results are still very limited in complexity but we show that our techniques successfully concentrate on the automatic exploration of very different solutions, and discover architectures known and unknown to expert designers, such as different types of adders, the carry-save representation, or improved multipliers. This is a first step toward a class of arithmetic optimizers which sit on top of classic logic synthesizers.