Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Residue BDD and its application to the verification of arithmetic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking of datapaths based on canonical arithmetic expressions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
The future of logic synthesis and verification
Logic Synthesis and Verification
Induction-based gate-level verification of multipliers
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Introduction to the Special Issue on Verification of Arithmetic Hardware
Formal Methods in System Design
Verification of Arithmetic Circuits by Comparing Two Similar Circuits
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Implicit Verification of Structurally Dissimilar Arithmetic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Fast co-verification of HDL models
Microelectronic Engineering
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Verification of gate-level implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hard-to-verify arithmetic operators (e.g. multiplication), the use of different operand ordering, the incorporation of merged arithmetic with cross-operator implementations, and the employment of circuit transformations based on arithmetic relations. It is hence a peculiar problem that does not fit quite well into the existing RTL-to-gate equivalence checking methodology. In this paper, we propose a self-referential functional verification approach which uses the gate-level implementation of the arithmetic circuit under verification to verify itself. Specifically, the verification task is decomposed into a sequence of equivalence checking subproblems, each of which compare circuit pairs derived from the implementation under verification based on the proposed self-referential functional equations. A decomposition-based heuristic using structural information is employed to guide the verification process for better efficiency. Experimental results on a number of implementations of the multiply-add units and the inner product units with different architectures demonstrate the versatility of this approach.