Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Using BDDs to verify multipliers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Verification of Arithmetic Circuits by Comparing Two Similar Circuits
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Implicit Verification of Structurally Dissimilar Arithmetic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Self-referential verification of gate-level implementations of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Fast co-verification of HDL models
Microelectronic Engineering
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving constant-coefficient multiplier verification by partial product identification
Proceedings of the conference on Design, automation and test in Europe
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We propose a method based on unrolling the inductive definition of binary number multiplication to verify gate-level implementations of multipliers. The induction steps successively reduce the size of the multiplier under verification. Through induction, the verification of an n-bit multiplier is decomposed into n equivalence checking problems. The resulting equivalence checking problems could be significantly sped up by simple structural analysis. This method could be generalized to the verification of more general arithmetic circuits and the equivalence checking of complex data-path.