Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Equivalence checking of integer multipliers
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Induction-based gate-level verification of multipliers
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Verification of Arithmetic Circuits by Comparing Two Similar Circuits
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Logic synthesis and circuit customization using extensive external don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Proceedings of the Conference on Design, Automation and Test in Europe
ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Constant-coefficient multipliers are fundamental components in digital signal processing and arithmetic-based systems. Their verification, however, remains difficult and time-consuming. This is caused by the inability to identify the partial products from the number representation system of the constant. In this paper, we introduce an efficient number representation system as an observation on how modern synthesizers interpret constants. We also propose a robust and efficient partial product identification algorithm to improve the verification process. Experimental results show that our algorithm not only reduces the number of failing cases of the verification to one third but also speeds up the verification process by at least an average of 25%.