Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Implicit Verification of Structurally Dissimilar Arithmetic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving constant-coefficient multiplier verification by partial product identification
Proceedings of the conference on Design, automation and test in Europe
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In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut points and thus dramatically improve the backward substitution process, (2) a layered-backward substitution algorithm to reduce the number of substitutions, and (3) Multiplicative Power Hybrid Decision Diagrams(*PHDDs) as our word-level representation rather than *BMD in Hamaguchi's approach. Experimental results show that our approach can efficiently check the equivalence of two integer multipliers. To verify the equivalence of a 32 x 32 array multiplier versus a 32 x 32 Wallace tree multiplier, our approach takes about 57 CPU seconds using 11 Mbytes, while Stanion's approach took 21027 seconds using 130 MBytes. We also show that the complexity of our approach grows cubically O(n3).