Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Using BDDs to verify multipliers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Residue BDD and its application to the verification of arithmetic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Prove that a faulty multiplier is faulty!?
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Equivalence checking of integer multipliers
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Self-referential verification of gate-level implementations of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Induction-based gate-level verification of multipliers
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
The K*BMD: A Verification Data Structure
IEEE Design & Test
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Fault-based attack of RSA authentication
Proceedings of the Conference on Design, Automation and Test in Europe
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BDD-based approaches cannot handle some arithmetic functions such as multiplication efficiently, while Binary Moment Diagrams proposed by Bryant and Chen provide compact representations for those functions. They reported a BMD-based polynomial-time algorithm for verifying multipliers. This approach requires high-level information such as specifications to subcomponents. This paper presents a new technique called backward construction which can construct BMDs directly from circuit descriptions without any high-level information. The experiments show that the computation time for verifying for n-bit multipliers is approximately n^4. We have successfully verified 64-bit multipliers of several type in 3-6 hours with 40 Mbyte of memory on SPARCstation10/51. This result outperforms previous BDD-based approaches for verifying multipliers.