Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Formal verification of integer multipliers was an open problem for a long time as the size of any reduced ordered binary decision diagram (BDD) [1] which represents integer multiplication is exponential in the width of the operands [2]. In 1995, Bryant and Chen [4] introduced multiplicative binary moment diagrams (*BMD) which are a canonical data structure for pseudo Boolean functions allowing a linear representation of integer multipliers. Based on this data structure, Bryant/Chen [4] and Hamaguchi et.al. [5] experimentally showed that integer multipliers up to a word size of 64 bits can be formally verified. However, all these results only handle the problem of proving a faultless integer multiplier to be correct. But, what happens if the multiplier is faulty? Does the backward construction method of Hamaguchi et.al. stop after a short time? After what time can I be sure that the integer multiplier under consideration is faulty? In this paper, we show that these questions are relevant in practice. In particular, we investigate simple add-step multipliers and show that simple design errors can lead to exponential growth of the *BMDS occuring during backward construction. This proves that the backward construction method can only be applied as filter during formal logic combinational verification unless sharp upper bounds for the sizes of the *BMDs occuring during the backward construction have been proven for the various circuit types as Keim et.al. [6] did it for Wallace Tree multipliers.