Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A synthesis-based test generation and compaction algorithm for multifaults
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Logic Synthesis for Testability
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimal low powerX OR gate decomposition
Proceedings of the 37th Annual Design Automation Conference
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Power minimization of FPRM functions based on polarity conversion
Journal of Computer Science and Technology
Functionally linear decomposition and synthesis of logic circuits for FPGAs
Proceedings of the 45th annual Design Automation Conference
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