Field-programmable gate arrays
Field-programmable gate arrays
Electronic logic systems (3rd ed.)
Electronic logic systems (3rd ed.)
Multilevel logic synthesis for arithmetic functions
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Technology-dependent transformations for low-power synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimal low powerX OR gate decomposition
Proceedings of the 37th Annual Design Automation Conference
Representations of Discrete Functions
Representations of Discrete Functions
Novel synthesis and optimization of multi-level mixed polarity Reed-Muller functions
Journal of Computer Science and Technology
Techniques for dual forms of Reed-Muller expansion conversion
Integration, the VLSI Journal
Onset based optimization of multi-level mixed polarity Reed-Muller functions
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
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For an n-variable Boolean function, there are 2n fixed polarity Reed-Muller (FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions is presented and the polarity conversion is introduced to minimize the power for FPRM functions. Based on searching the best polarity for low power dissipation, an optimal algorithm is proposed and implemented in C. The algorithm is tested on seven single output functions from MCNC benchmark circuits. The experimental results are shown in this paper.