Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Designing for scan test of high performance embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
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The PowerPC 603 microprocessor is a powerful low-cost implementation of the PowerPC architecture specification. The structured design, logic verification and test data generation methodologies of the 603 are presented in this paper. The success of these methodologies has been demonstrated by meeting the 603's aggressive time-to-market goals.