Parallel Signature Analysis Design with Bounds on Aliasing
IEEE Transactions on Computers
Analysis and Design of Optimal Combinational Compactors
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Efficient unknown blocking using LFSR reseeding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
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This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature Registers (MISR). The proposed scheme guarantees no coverage loss for the modeled faults. The proposed hybrid scheme can also be tuned to observe any user-specified percentage of responses for controlling the coverage loss for un-modeled faults. The experimental results demonstrate that, in comparison with a space compactor or an unknown-blocking MISR alone, the hybrid compaction scheme achieves a lower coverage loss without demanding more test-data volume. In addition, we propose a quantitative approach to estimate the required percentage of observable responses for the proposed scheme, directly based on a test-quality metric of un-modeled faults.