Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
X-Tolerant Test Response Compaction
IEEE Design & Test
A Class of Linear Space Compactors for Enhanced Diagnostic
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Survey of Test Vector Compression Techniques
IEEE Design & Test
Hierarchical Test Compression for SoC Designs
IEEE Design & Test
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The emergence of System-on-Chip (SoC) devices has led to a complex on-chip interconnect structure that consumes significant area. Distributed compaction is a test response compaction scheme for an SoC that aims at reducing the area occupied for the purpose of testing the chip. This technique involves the design of compactors for individual cores on the chip. These are interconnected suitably to achieve the required functionality while reducing the area overhead by decreasing the length and the number of interconnects that are routed from scan chain outputs to the output pins. The distributed compaction technique matches the performance of an X-Compactor in terms of error detection and X-masking.