Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Testing by Feedback Shift Register
IEEE Transactions on Computers
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Construction and Analysis of Augmented Time Compactors
Journal of Electronic Testing: Theory and Applications
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
An earlier paper [1] describes a method of identifying failing test patterns (when signature analysis is used) through operations on the faulty and the fault-free signatures. The major drawback of this method is the complexity of identi fying three or more failing tests. This paper shows a method of operating on signatures from a cycling register such that the complexity of identifying multiple failing tests is comparable to that of identifying a single failing test. The method has some interesting aliasing charact eristics. The paper shows the probability of aliasing and suggests how it can be kept relatively small.