Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
An Adder Using Charge Sharing and its Application in DRAMs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Implementing branch-predictor decay using quasi-static memory cells
ACM Transactions on Architecture and Code Optimization (TACO)
High-level synthesis using computation-unit integrated memories
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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The desire to enhance memory bandwidth in high-performance computing components is overwhelming, and early attempts to combine large memories with high-performance logic in a single silicon integrated circuit are numerous. However existing implementations of a combined (merged) memory-logic technology are unsatisfactory (because of high cost) and complicated (because the technologies used for high-performance logic and high-density memory are disparate). The research reported here will explain the joint technology development of two corporations working on a merged memory-logic technology in terms of:1) memory cell design comparisons 2) transistor and capacitor specifications, 3) process technology tradeoffs, and 4) circuit simulations.