An Adder Using Charge Sharing and its Application in DRAMs

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ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

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Abstract

This paper develops a novel technique, which uses charge sharing as a method to perform addition in memory arrays. DRAM cells are conventionally used as storage elements and their data read through charge sharing. In our approach, DRAM cells are used as arithmetic units, thus saving area and power consumption in system-on-silicon applications. An adder in DRAM is designed, and its HSPICE simulation results are presented to show the viability of the proposed scheme.