An Effective Multi-Chip BIST Scheme
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Journal of Electronic Testing: Theory and Applications
BISTing Datapaths under Heterogeneous Test Schemes
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Design and test space exploration of transport-triggered architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
Journal of Electronic Testing: Theory and Applications
Power-/Energy Efficient BIST Schemes for Processor Data Paths
IEEE Design & Test
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Effective BIST Scheme for Arithmetic Logic Un i t s
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
On-Line Monitor Design of Finite-State Machines
Journal of Electronic Testing: Theory and Applications
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation
Journal of Electronic Testing: Theory and Applications
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