Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Error-Control Coding in Computers
Computer
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 3. Internationale GI/ITG/GMA-Fachtagung
Is High-Level Test Synthesis Just Design for Test?
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ Testing of CMOS Opens: An Experimental Study
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Many Faces of Test Synthesis
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Advantages of High-Level Test Synthesis over Design for Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Can Concurrent Checkers Help BIST?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
IDDQ Testing in CMOS Digital ASIC's - Putting it All Together
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
The Cost of Quality: Reducing ASIC Defects with IDDQ At-Speed Testing and Increased Fault Coverage
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Modular LSI Control Logic Design with Error Detection
IEEE Transactions on Computers
IBM Journal of Research and Development
A realistic fault model and test algorithms for static random access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Continuous signature monitoring: low-cost concurrent detection of processor control errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault simulation of unconventional faults in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Using on-chip fault detection measures the Fail-Stop ControllerAE11 was developed for safety critical applicationsaiming at high volume production of automotive and railwayelectronics. The trade-off between high defect coverage,short reaction time to faults and low chip areaoverhead results in a combination of Concurrent Checking,Built-In Self-Test and Built-In Current-Monitoring (I DDQ -Test).