Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Detection of Unidirectional Multiple Errors Using Low-Cost Arithmetic Codes
IEEE Transactions on Computers
An Algebraic Model of Arithmetic Codes
IEEE Transactions on Computers
Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
An Error-Detecting Binary Adder: A Hardware-Shared Implementation
IEEE Transactions on Computers
Notes on the Arithmetic BN Modulo A Codes
IEEE Transactions on Computers
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It is widely known that a computer adder can be checked by a completely independent circuit using check symbols that are residues of the numbers modulo some base. This paper describes such a residue checking system and shows, moreover, that independent adding and checking circuits are possible only with systems of this type. The discussion includes a method of handling residue-class check symbols when overflow occurs.