A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Effective BIST Scheme for Arithmetic Logic Units
Proceedings of the IEEE International Test Conference
An Effective BIST Scheme for Ring-Address Type FIFOs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testability metrics for synthesis of self-testable designs and effective test plans
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
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Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regular counter-generated deterministic test set for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor or DSP datapaths. The BIST scheme provides near complete coverage with respect to the stuck-at fault model for any datapath width as it is verified by a comprehensive set of experiments. The proposed BIST scheme uses the same Test Pattern Generation (counters) and Output Data Evaluation (accumulators) resources as in our earlier BIST schemes for multiplier/accumulator pairs, thus completing a deterministic counter-based datapath BIST architecture.