On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
A Compression-Driven Test Access Mechanism Design Approach
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing
ATS '04 Proceedings of the 13th Asian Test Symposium
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Proceedings of the conference on Design, automation and test in Europe
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.