On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
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We address the problem of power-constrained testing of core based system chips. Built-in self-test methodology for testing individual cores is assumed, and sharing of test resources (pattern generators and signature registers) among cores is permitted. We consider a scenario where the system integrator is dealing with ``soft'' or "firm cores" for which the final realization has not been frozen and the flexibility of module selection rests with the integrator. We argue that advantage can be taken of this flexibility in coming up with a power-constrained test plan. Since scheduling of test sessions also affects power dissipation in a crucial way, we present an algorithm for simultaneous module selection and test scheduling. Our objective is to minimize the test application time treating the test area overhead and total power dissipation as constraints. We report the results of our implementation of a test planner on two examples.