Testing and build-in self-test - a survey

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Journal of Systems Architecture: the EUROMICRO Journal

A parameterized graph-based framework for high-level test synthesis

Integration, the VLSI Journal

Simultaneous reduction in test data volume and test time for TRC-reseeding

Proceedings of the 17th ACM Great Lakes symposium on VLSI

A test set embedding approach based on twisted-ring counter with few seeds

Integration, the VLSI Journal

Evolution of self-diagnosing hardware

ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware

Reversible online BIST using bidirectional BILBO

Proceedings of the 7th ACM international conference on Computing frontiers