Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Testing and build-in self-test - a survey
Journal of Systems Architecture: the EUROMICRO Journal
Digital Design
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Low power dissipation (PD) during testing is emerging as one of the major objectives of a built-in self-test (BIST) designer. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power BIST scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable test pattern generators (TPGs), (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. Results indicate that the total power dissipated, the average power per test vector and the peak PD during testing can be reduced up to 73%, 27% and 36% respectively with respect to earlier schemes, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.