Testing and build-in self-test - a survey
Journal of Systems Architecture: the EUROMICRO Journal
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
Fault Testing for Reversible Circuits
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Testing for Missing-Gate Faults in Reversible Circuits
ATS '04 Proceedings of the 13th Asian Test Symposium
Test Generation and Fault Localization for Quantum Circuits
ISMVL '05 Proceedings of the 35th International Symposium on Multiple-Valued Logic
Introduction to reversible computing: motivation, progress, and challenges
Proceedings of the 2nd conference on Computing frontiers
A Family of Logical Fault Models for Reversible Circuits
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Conservative Logic Elements and Their Universality
IEEE Transactions on Computers
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Toffoli network synthesis with templates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Test generation for reversible circuits is currently gaining interest due to its feasibility towards quantum implementation and asymptotically zero-power dissipation. A novel BIST (Built-In-Self-Test) method for reversible circuits is proposed in this paper. New bidirectional D-latch and D-flipflop designs are introduced. A Reversible BILBO (Built-in-Logic-Block-Observer) based on conventional BILBO is designed to facilitate the BIST procedure. The complete test procedure is executed and experimental results are analyzed for both stuck at and missing gate faults (MGF) with 100% fault coverage.