High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Scheduling of behavioral VHDL by retiming techniques
EURO-DAC '94 Proceedings of the conference on European design automation
A methodology for guided behavioral-level optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Behavioral Synthesis and Component Reuse with VHDL
Behavioral Synthesis and Component Reuse with VHDL
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Matisse: An Architectural Design Tool for Commodity ICs
IEEE Design & Test
The MIMOLA design system: Detailed description of the software system
DAC '79 Proceedings of the 16th Design Automation Conference
Automated exploration of the design space for register-transfer (rt) systems.
Automated exploration of the design space for register-transfer (rt) systems.
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Although very popular and largely wanted, behavioral synthesis was never widely accepted by designers. This paper analyzes the reasons for this failure and introduces a new generation of behavioral synthesis tools with more practical synthesis schemes. The main breakthrough of this new generation is the redefinition of the behavioral synthesis flow to better profit from the power of modern RTL and FSM synthesis. The synthesis results for two large design examples: a 2-million transistor ATM shaper and a motion estimator for a video codec (H261 standard) are shown. They illustrate the effectiveness of this new approach when compared with RT-level design methodologies.