IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Partitioned bus coding for energy reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Proceedings of the 2006 international symposium on Physical design
A path based modeling approach for dynamic power estimation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized design of interconnected bus on chip for low power
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
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Ultra-deep submicron technology and system-on-chip have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are: 1) the self transition activities on the signal lines and 2) the coupled transition activities of the lines. However, there has been no easy way of optimizing 1 and 2 simultaneously at an early stage of the synthesis process. In this paper, we propose a new (on-chip) bus synthesis algorithm to minimize the total sum of 1 and 2 in the microarchitecture synthesis. Specifically, unlike the previous approaches in which 1 and 2 are minimized sequentially without any interaction between them, or only one of them is minimized, we, given a scheduled dataflow graph to be synthesized, minimize 1 and 2 simultaneously by formulating and solving the two important issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of signal lines in each bus, both of which are the most critical factors that affect the results of 1 and 2. Experimental results on a number of benchmark problems show that the proposed integrated low-power bus synthesis algorithm reduces power consumption by 24.8%, 40.3%, and 18.1% on average over those in (Chang and Pedram 1995, for minimizing 1 only), (Shin and Sakurai 2001, for 2 only) and (Shin and Sakurai 2001 and Chang and Pegram 1995, for 1 and then 2), respectively.