Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Coupling-aware high-level interconnect synthesis [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power bus encoding using an adaptive hybrid algorithm
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
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For VLSI design in deep submicron technology, the bus energy reduction has become more and more important. This paper studies the bus partition scheme for the Transition Pattern Coding (TPC). The genetic algorithm based approach is used. A closed-form expression is derived to calculate the energy dissipation for the partitioned bus with TPC coding. A general bus model with coupling capacitance is considered during the energy estimation and optimization. The resulted partitioned bus coding reduces the encoding and decoding complexity of the original TPC. The experimental results show that the TPC with careful bus partitioned saves up to 16.9% the energy of the TPC with random bus partition.