Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Parallel and Distributed Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned bus coding for energy reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transition reduction in memory buses using sector-based encoding techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Supporting faulty banks in NUCA by NoC assisted remapping mechanisms
The Journal of Supercomputing
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Network-on-chip (NoC) architectures must deliver good latency-through put performance in the face of tight power and area budgets. However, in high-performance chip design, a significant design challenge is how to fulfill the requirements of circuit noise elimination, since the faults will slow down performance and dissipate much of the overall system power. This paper presents a simple coding scheme for reducing power dissipation, crosstalk noise, and crosstalk delay on the bus while simultaneously detecting errors at runtime. It uses a simple bus-invert encoding technique to reduce the prohibited transitions in terms of crosstalk noise and power dissipation. We also design a corresponding detector to detect errors at the input of the NoC routers. It can save energy by interrupting communications without storing and routing the packets when errors occur during transmissions. The experimental results for various multimedia applications show significant reduction in the number of patterns that are most likely to produce crosstalk errors. The results also show that it is attractive in terms of cost to apply the detecting logic to routers in the NoC with respect to the power consumption.