Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Narrow bus encoding for low power systems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Minimizing power across multiple technology and design levels
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimum positioning of interleaved repeaters In bidirectional buses
Proceedings of the 40th annual Design Automation Conference
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses
Proceedings of the 2004 international symposium on Low power electronics and design
Resource-constrained low-power bus encoding with crosstalk delay elimination
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Routing of analog busses with parasitic symmetry
Proceedings of the 2005 international symposium on Physical design
Energy optimization in memory address bus structure for application-specific systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Formal derivation of optimal active shielding for low-power on-chip buses
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
A variation-aware low-power coding methodology for tightly coupled buses
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned bus coding for energy reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized design of interconnected bus on chip for low power
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
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In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.