Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Proceedings of the conference on Design, automation and test in Europe
Wire Placement for Crosstalk Energy Minimization in Address Buses
Proceedings of the conference on Design, automation and test in Europe
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Coupling-aware high-level interconnect synthesis [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we firstly propose an on-chip bus power consumption model, which includes the self transition power dissipated on the signal lines and the coupled transition power dissipated between every two signal lines. And then a new heuristic algorithm is proposed to determine a physical order of signal lines in bus. Experimental results show an average power saving 26.85%.