Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Value-based bit ordering for energy optimization of on-chip global signal buses
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Wire topology optimization for low power CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized design of interconnected bus on chip for low power
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
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We propose a novel approach to bus energy minimization that targetscrosstalk effects. Unlike previous approaches, we try to reduceenergy through capacitance optimization, by ad opting non-uniformspacing between wires. This allows reduction of power,and at the same time takes into account signal integrity. Therefore,performance is not degraded. Results show that the methodsaves up to 30% of total bus energy at no cost in performanceor complexity of the design (no encoding-decoding circuitry isneeded), and limited cost in area.