Wire topology optimization for low power CMOS

Authors:
Paul Zuber;Othman Bahlous;Thomas Ilnseher;Michael Ritter;Walter Stechele
Affiliations:
Technology Aware Design, Interuniversity Microelectronics Center, Löwen, Belgium and Lehrstuhl für Integrierte Systeme, Technische Universitä München, München, Germany;AIM MC ATM MD, Infineon Technologies AG, Neubiberg, Germany;Lehrstuhl Entwurf Mikroelektronischer Systeme, Universität Kaiserslautern, Kaiserslautern, Germany;Zentrum Mathematik, Technische Universitä München, Garching bei München, Germany;Lehrstuhl fü Integrierte Systeme, Technische Universitä München, München, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an industry-proven design flow. Wire power reductions of up to 9.55% for modern multiprocessor benchmarks with tight area constraints are demonstrated, twice as much as approaches that do not take switching activities into account. Timing is not adversely affected, and the yield limit is slightly improved.