Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Wire Placement for Crosstalk Energy Minimization in Address Buses
Proceedings of the conference on Design, automation and test in Europe
Error Correcting Codes for Crosstalk Effect Minimization
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling-aware high-level interconnect synthesis [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire topology optimization for low power CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With decreasing feature size on silicon, the coupling capacitances of buses grow rapidly causing a significant impact on the power consumption of the whole chip. Thus, buses should be designed and optimized to dissipate less power without sacrificing performance. In this paper, we address this problem by simultaneously optimizing wire permutation, inversion and spacing (space between consecutive wires) using a combination of optimal as well as genetic algorithms. Unlike previous studies, our approach is applicable to not only address buses (behave more regularly), but also instruction buses of microprocessors. For the spacing problem, an algorithm is presented which determines the optimal solution instead of applying time consuming heuristic algorithms as presented in [Wire Placement for Crosstalk Energy Minimization in Address Bus]. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. We simulate different combinations among permutation, spacing, and inversion. Integrated all optimization techniques together, our approach can save energy up to 68% for the best case and 58% on average while only increasing the total wire space by about 50% (compared to a bus with minimal spacing between adjacent wires for a particular technology).