The optimal wire order for low power CMOS

Authors:
Paul Zuber;Peter Gritzmann;Michael Ritter;Walter Stechele
Affiliations:
Institute for Integrated Systems, TU München, Germany;Institute for Combinatorial Geometry, TU München, Germany;Institute for Combinatorial Geometry, TU München, Germany;Institute for Integrated Systems, TU München, Germany
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.