Low power design flow and libraries
Low power design in deep submicron electronics
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Low Power Digital CMOS Design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Interconnection analysis for standard cell layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of the maximum delay of global interconnects during layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
The optimal wire order for low power CMOS
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Wire load has become an important variable for power and timing optimization. As standard cell geometries are shrinking and average wirelength increases due to increasing design complexities wire capacitance has become dominant over gate capacitance. However the wire load of a net not only depends on wirelength but also on which metal layer a net is routed. In this paper we investigate the characteristics of metal layers and propose a power driven routing scheme, which exploits the different metal layer properties in deep submicron semicustom design flows. Layer assignment for final routing will be done according to the switching activity of a net and the layer characteristics. In section 3 we describe the investigation of the characteristics of routing layers. A parameter for the validation of metal layers for use in routing for low-power is derived. In sections 4 and 5 an objective function for power driven routing and the layer assignment methodology is described.