Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low Power Design in Deep Submicron Electronics
Low Power Design in Deep Submicron Electronics
Low Power Digital CMOS Design
Exploiting Metal Layer Characteristics for Low-Power Routing
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
The optimal wire order for low power CMOS
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key: if a capacitance is not switched often, it may be high. If it is frequently switched, it should be minimized in order to reduce power consumption. This can be done by an algorithm based on forces that automatically optimizes the position and length of every single wire segment in a routed design. The forces are proportional to the toggle activities derived from a gate level simulation. The novelty is that this allows to iteratively find a new topology for the wire segments. Our algorithm takes as input an already given, grid routed layout.